1. Field of the Invention
The present invention relates to switch mode power supplies and driving methods, particularly for efficient RF amplification, as well as amplifier structures using the same.
2. State of the Art
As is well-known, the efficiency of power amplifiers such as those used in wireless telecommunications can be increased substantially using a variable power supply instead of a fixed power supply. In this application, as well as a wide variety of other applications, a switch mode power supply may be used to efficiently perform DC-to-DC conversion from a fixed DC power supply input to a variable supply output.
One example of a known switch mode power supply (in particular a buck converter) and associated driver circuit is shown in FIG. 1. A transistor switch Q5 (in this instance a N-FET device) is alternately switched ON and OFF in accordance with some duty cycle during an ON portion of which an operational voltage VDD is coupled to an output filter. The output filter may take the form of a series LC circuit, where the output voltage is taken at a circuit node N in-between an inductor L1 and a capacitor C2. In addition, a Schottky diode D1 is provided to clamp the negative voltage spike induced in the inductor when the switch is turned OFF, forcing the output voltage positive and protecting the transistor Q5.
A driving circuit for the buck converter includes a high-side driver/level shifter 110 and a low-side driver 120.
The low-side driver 120 includes a transistor switch Q2 coupled between a gate electrode of the transistor Q5 and a reference potential, e.g., ground. During the OFF portion of the duty cycle, the transistor Q2 is turned on, grounding the gate of the transistor Q5, causing it to turn off. A gate electrode of the transistor Q2 may be driven directly by a control circuit or, as in the illustrated embodiment, the drive level applied to the gate electrode may be controlled using a transistor/resistor combination. Where the Q2 source electrode needs to be biased negative with respect to ground, the transistor Q6 and the resistor R3 provide level shifting in the negative direction.
The high-side driver/level shifter 110 includes a transistor Q7 (e.g., a P-FET) coupled between an operational voltage VSS (VSS>VDD) and the gate of the transistor Q5. During the ON portion of the duty cycle, the transistor Q7 is turned on, raising the gate of the transistor Q5 and causing it to turn on. A remaining portion of the high-side driver/level shifter performs a level-shifting function, allowing the transistor Q7 to be controlled using a logic-level signal. In particular, a resistive voltage divider network (series-connected resistors R1 and R2) is coupled from the voltage VSS through a transistor Q1 to ground. An intermediate node between the resistors R1 and R2 is coupled to a gate electrode of the transistor Q7. When the transistor Q1 is turned on, current flows through the voltage divider, causing a voltage to be applied to the gate of the transistor Q7 sufficient to turn it on.
One of the challenges presented in designing the level-shifting circuit is to maintain efficiency. A capacitor C1 coupled in parallel with the resistor RI improves efficiency.
More particularly, the driving impedance for the gate of transistor Q7 must be minimized to rapidly switch on the transistor Q7. The turn-off time, on the other hand, can be as long as the period of the minimum allowed duty cycle for the power supply.
Without the capacitor C1, the driving impedance in the ON direction for the gate of the transistor Q7 is the ON resistance, Rds, of the transistor Q1 plus the resistance R1. It would be easy to minimize this impedance by making the resistor R1 equal to zero. However, the DC current through R1 and R2 would then be very high for as long as the transistor Q1 is ON. The value of the resistor R2 is chosen such that its combination with the gate-to-source capacitance, Cgs, of the transistor Q7 makes an RC time constant low enough to meet the minimum duty cycle requirement.
Adding the capacitor C1 momentarily lowers the drive impedance for the gate of the transistor Q7 down to the sum of the ON resistance of the transistor Q1 and the effective series resistance (ESR) of the capacitor C1. The capacitance Cgs of the transistor Q7 can then be charged up rapidly. The value of the capacitor C1 may be chosen to be approximately equal to the value of the capacitance Cgs of the transistor Q7. The value of the resistor R1 can then be made as high as that of the resistor R2, which makes the DC current smaller and increases efficiency.
A waveform diagram illustrating operation of the circuit of FIG. 1 is shown in FIG. 2, showing waveforms applied to the gate electrodes of the transistors Q1 and Q6 in order to produce a waveform of the desired duty cycle on the gate electrode of the transistor Q5. As may be observed, the gate electrode of the transistor Q5 goes high when the gate electrode of the transistor Q1 goes high, and is driven low when the gate electrode of the transistor Q6 is driven low. To ensure non-overlapping operation of the transistors Q7 and Q2, the gate electrode of the transistor Q6 is raised (turning the transistor Q6 off) some small time before the gate electrode of the transistor Q1 is raised (turning the transistor Q1 on). Similarly, the gate electrode of the transistor Q1 is lowered (turning the transistor Q1 off) some small time before the gate electrode of the transistor Q6 is lowered (turning the transistor Q6 on).
The power consumption of the circuit of FIG. 1 is greater than desired. In particular, considerable power is dissipated by the resistive voltage divider network during the time that the gate electrode of the transistor Q1 is high.
Furthermore, the upper frequency limit at which the circuit of FIG. 1 can be operated is lower than desired. Where the switch mode power supply is used in next-generation wireless telecommunications applications, for example, it is desirable for the switch mode power supply to be able to track envelope variations of the telecommunications signal, requiring in some instances switching speeds upward of 2 MHz.
French Patent 2,768,574 also describes a switched-mode power amplifier arrangement. Referring to FIG. 9, in this arrangement, the power amplifier circuit comprises a DC-to-DC converter 20 and a power amplifier 30. The DC-to-DC converter 20 includes a pulse-width modulator 22, a commutator/rectifier 24 and a filter 26.
The pulse-width modulator 22 is coupled to receive a DC-to-DC command input signal from a signal input terminal 21, and is arranged to apply a pulse-width-modulated signal to the commutator/rectifier 24. The commutator/rectifier 24 is coupled to receive a DC-to-DC power supply input signal from a signal input terminal 25, and is also coupled to apply a switched signal to filter 26. The filter 26 in turn applies a filtered switched signal 28 in common to multiple stages of the power amplifier 30.
A circuit of the foregoing type is substantially limited by the frequency of the pulse-width modulator. In addition, common control of multiple power amplifier stages in the manner described may prove disadvantageous as described more fully hereinafter.